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| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2016-09-30 13:57:12 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-07 18:18:14 +0200 |
| commit | 135eae91d57354bc1bfae04056e539d3ce1f7f9c (patch) | |
| tree | 52b9a2d429ac437f570c08e9b3c078a460f90e83 /src/drivers | |
| parent | 9344bde4fedfa7caed35aaa45d25c7184edcf4ae (diff) | |
| download | coreboot-135eae91d57354bc1bfae04056e539d3ce1f7f9c.tar.xz | |
soc/intel/apollolake: Implement stage cache to improve resume time
This patch enables stage cache to save ~40ms during S3 resume.
It saves ramstage in the stage cache and restores it on resume
so that ramstage does not have to reinitialize during the
resume flow. Stage cache functionality is added to postcar stage
since ramstage is called from postcar.
BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for Reef and tested ramstage being cached
Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16833
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 3986fe68d1..beeec7cee9 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -37,6 +37,8 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with |