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authorLee Leahy <leroy.p.leahy@intel.com>2016-05-04 13:13:20 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-09 18:44:47 +0200
commit148762110c8a00c88b8e0326ec69dc7392bf3739 (patch)
tree75073d645ac062177a466e9451db8796fd1fdde8 /src/drivers
parenta63398059bdd5911e9e5e670873183cdb376acf7 (diff)
downloadcoreboot-148762110c8a00c88b8e0326ec69dc7392bf3739.tar.xz
drivers/uart: Enable override for input clock divider
Allow the platform to override the input clock divider by adding the uart_input_clock_divider routine. This routine combines the baud-rate oversample divider with any other input clock divider. The default routine returns 16 which is the standard baud-rate oversampling value. A platform may override this default "weak" routine by providing a new routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/uart/Kconfig7
-rw-r--r--src/drivers/uart/uart8250io.c10
-rw-r--r--src/drivers/uart/uart8250mem.c3
-rw-r--r--src/drivers/uart/util.c17
4 files changed, 33 insertions, 4 deletions
diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index ae3e81adb1..cb129b0643 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -13,6 +13,13 @@ config DRIVERS_UART_8250IO
config NO_UART_ON_SUPERIO
def_bool n
+config UART_OVERRIDE_INPUT_CLOCK_DIVIDER
+ boolean
+ default n
+ help
+ Set to "y" when the platform overrides the uart_input_clock_divider
+ routine.
+
config DRIVERS_UART_8250MEM
bool
default n
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index 0974005a81..69244f58df 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -30,8 +30,12 @@
/* Nominal values only, good for the range of choices Kconfig offers for
* set of standard baudrates.
*/
-#define BAUDRATE_REFCLK (115200)
-#define BAUDRATE_OVERSAMPLE (1)
+
+/* Multiply the maximim baud-rate by the default oversample rate to compute
+ * the default input clock to the UART. The uart_baudrate_divisor divides
+ * by the oversample clock to determine the final baud-rate.
+ */
+#define BAUDRATE_REFCLK (115200 * 16)
/* Expected character delay at 1200bps is 9ms for a working UART
* and no flow-control. Assume UART as stuck if shift register
@@ -112,7 +116,7 @@ void uart_init(int idx)
{
unsigned int div;
div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK,
- BAUDRATE_OVERSAMPLE);
+ uart_input_clock_divider());
uart8250_init(uart_platform_base(idx), div);
}
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index 2f2bd2df56..4b87756d0b 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -117,7 +117,8 @@ void uart_init(int idx)
return;
unsigned int div;
- div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16);
+ div = uart_baudrate_divisor(default_baudrate(),
+ uart_platform_refclk(), uart_input_clock_divider());
uart8250_mem_init(base, div);
}
diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c
index 4121f60852..5e8d223252 100644
--- a/src/drivers/uart/util.c
+++ b/src/drivers/uart/util.c
@@ -42,3 +42,20 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate,
{
return (1 + (2 * refclk) / (baudrate * oversample)) / 2;
}
+
+#if !IS_ENABLED(CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER)
+unsigned int uart_input_clock_divider(void)
+{
+ /* Specify the default oversample rate for the UART.
+ *
+ * UARTs oversample the receive data. The UART's input clock first
+ * enters the baud-rate divider to generate the oversample clock. Then
+ * the UART typically divides the result by 16. The asynchronous
+ * receive data is synchronized with the oversample clock and when a
+ * start bit is detected the UART delays half a bit time using the
+ * oversample clock. Samples are then taken to verify the start bit and
+ * if present, samples are taken for the rest of the frame.
+ */
+ return 16;
+}
+#endif