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authorFrans Hendriks <fhendriks@eltan.com>2020-11-20 10:52:39 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-11-22 22:17:43 +0000
commitc022a795033062ed1b1908d18fa419444e42aceb (patch)
tree7299ab7501a3971fc78f2610efc90be1d5281a6c /src/drivers
parent335eb1219c73032eee92462f76d508233fb97b55 (diff)
downloadcoreboot-c022a795033062ed1b1908d18fa419444e42aceb.tar.xz
drivers/intel/fsp1_1: Add function to report FSP-T output
This allows to compare the FSP-T output in %ecx and %edx to coreboot's CAR symbols. Tested on Facebook FBG1701 Change-Id: Ice748e542180f6e1dc1505e7f37b6b6c68772bda Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/intel/fsp1_1/Makefile.inc1
-rw-r--r--src/drivers/intel/fsp1_1/cache_as_ram.S13
-rw-r--r--src/drivers/intel/fsp1_1/fsp_report.c27
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/util.h1
4 files changed, 42 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 5fc100aa4b..abac7fba17 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -9,6 +9,7 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c
bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S
bootblock-y += fsp_util.c
bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S
+bootblock-y += fsp_report.c
romstage-y += car.c
romstage-y += fsp_util.c
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
index b5b47ce9a6..f2d29aa4a8 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.S
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -145,6 +145,14 @@ CAR_init_done:
* mm1: high 32-bits of TSC value
*/
+ /*
+ * temp_memory_start/end reside in the .bss section, which gets cleared
+ * below. Save the FSP return value to the stack before writing those
+ * variables.
+ */
+ push %ecx
+ push %edx
+
/* clear .bss section */
cld
xor %eax, %eax
@@ -154,6 +162,11 @@ CAR_init_done:
shrl $2, %ecx
rep stosl
+ pop %edx
+ movl %edx, temp_memory_end
+ pop %ecx
+ movl %ecx, temp_memory_start
+
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
diff --git a/src/drivers/intel/fsp1_1/fsp_report.c b/src/drivers/intel/fsp1_1/fsp_report.c
new file mode 100644
index 0000000000..884218d7f7
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/fsp_report.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/symbols.h>
+#include <console/console.h>
+#include <fsp/util.h>
+
+/* filled in assembly after FSP-T ran */
+uintptr_t temp_memory_start;
+uintptr_t temp_memory_end;
+
+void report_fsp_output(void)
+{
+ const struct region fsp_car_region = {
+ .offset = temp_memory_start,
+ .size = temp_memory_end - temp_memory_start,
+ };
+ const struct region coreboot_car_region = {
+ .offset = (uintptr_t)_car_region_start,
+ .size = (uintptr_t)_car_region_size,
+ };
+ printk(BIOS_DEBUG, "FSP: reported temp_mem region: [0x%08lx,0x%08lx)\n",
+ temp_memory_start, temp_memory_end);
+ if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) {
+ printk(BIOS_ERR, "Wrong CAR region used!\n");
+ printk(BIOS_ERR, "Adapt DCACHE_RAM_BASE and DCACHE_RAM_SIZE to match FSP-T\n");
+ }
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 41ffedde1d..cab867a68d 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -31,6 +31,7 @@ void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
void *get_first_resource_hob(const EFI_GUID *guid);
void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
uint64_t new);
+void report_fsp_output(void);
/* Return version of FSP associated with fih. */
static inline uint32_t fsp_version(FSP_INFO_HEADER *fih)