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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-28 15:04:17 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-30 06:00:57 +0000 |
| commit | dc34a9d6de6ab21a1f1ed1a6cba142585c092045 (patch) | |
| tree | af36248a9cbadbbd06a5510bd285d416c658441e /src/drivers | |
| parent | ce51d6d9d1ba9d49d0176f821c639aa2384f5582 (diff) | |
| download | coreboot-dc34a9d6de6ab21a1f1ed1a6cba142585c092045.tar.xz | |
AGESA,binaryPI: Split romstage_main() to BSP and AP parts
BSP and AP have two distinct execution paths for romstage.
Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/amd/agesa/romstage.c | 34 |
1 files changed, 31 insertions, 3 deletions
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 0ecfeb2bb6..f9a8c9705a 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -40,7 +40,7 @@ static void fill_sysinfo(struct sysinfo *cb) agesa_set_interface(cb); } -void *asmlinkage romstage_main(unsigned long bist) +static void bsp_romstage_main(unsigned long bist) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -53,7 +53,7 @@ void *asmlinkage romstage_main(unsigned long bist) fill_sysinfo(cb); - if ((initial_apic_id == 0) && boot_cpu()) { + if (initial_apic_id == 0) { timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); @@ -101,5 +101,33 @@ void *asmlinkage romstage_main(unsigned long bist) run_postcar_phase(&pcf); /* We do not return. */ - return NULL; +} + +static void __noreturn ap_romstage_main(unsigned long bist) +{ + struct sysinfo romstage_state; + struct sysinfo *cb = &romstage_state; + + /* Enable PCI MMIO configuration. */ + amd_initmmio(); + + fill_sysinfo(cb); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + agesa_execute_state(cb, AMD_INIT_RESET); + + agesa_execute_state(cb, AMD_INIT_EARLY); + + /* Not reached. */ + halt(); +} + +asmlinkage void romstage_main(unsigned long bist) +{ + if (boot_cpu()) + bsp_romstage_main(bist); + else + ap_romstage_main(bist); } |