diff options
| author | robbie zhang <robbie.zhang@intel.com> | 2016-02-10 11:40:11 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-14 22:50:19 +0100 |
| commit | 13a2e949d5970b9ff09cdd7d8a3943f111538d83 (patch) | |
| tree | 975f3877d076ffaa6ffa7e471d98cc97fc9ac3ef /src/drivers | |
| parent | bedbd67e649796808421a6ed79bbb16be57f264d (diff) | |
| download | coreboot-13a2e949d5970b9ff09cdd7d8a3943f111538d83.tar.xz | |
Intel common: add microcode loading to romstage before fspmemoryinit
The intend is to seek upgraded microcode in RW section and load it
before Fsp memoryinit, to ensure any goodness in the microcode update,
especially related to memory configuration, can be applied earlier.
BUG=chrome-os-partner:50132
BRANCH=glados
TEST=Built and boot on kunimintus. Verified microcode gets reloaded.
Boot time impact is very minor.
CQ-DEPEND=CL:327170
Change-Id: I1a5df1d1efa25fb256743dca6a661c828263ec7c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7f700c1876e53194748d1d1c66637b9419b7086
Original-Change-Id: I7083ec6305af9e14a57d7b0cb1bd800cd9e22f44
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327193
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13688
Tested-by: build bot (Jenkins)
Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/intel/fsp1_1/romstage.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 7466575c82..bf84d662af 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -22,6 +22,7 @@ #include <boardid.h> #include <console/console.h> #include <cbmem.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/mtrr.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> @@ -49,6 +50,10 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) timestamp_add_now(TS_START_ROMSTAGE); + /* Load microcode before ram init */ + if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS)) + intel_update_microcode_from_cbfs(); + memset(&pei_data, 0, sizeof(pei_data)); /* Display parameters */ |