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authorJulius Werner <jwerner@chromium.org>2019-12-02 18:02:51 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-04 14:10:37 +0000
commit1c371572188a90ea16275460dd4ab6bf9966350b (patch)
tree5b9ad6854ce25f11ca516887fd85e614c3c28eb8 /src/drivers
parent41fe62b6dccd6be84e9d3685c73f1d8683af78de (diff)
downloadcoreboot-1c371572188a90ea16275460dd4ab6bf9966350b.tar.xz
mmio: Add clrsetbitsXX() API in place of updateX()
This patch removes the recently added update8/16/32/64() API and replaces it with clrsetbits8/16/32/64(). This is more in line with the existing endian-specific clrsetbits_le16/32/64() functions that have been used for this task on some platforms already. Rename clrsetbits_8() to clrsetbits8() to be in line with the new naming. Keep this stuff in <device/mmio.h> and get rid of <mmio.h> again because having both is confusing and we seem to have been standardizing on <device/mmio.h> as the standard arch-independent header that all platforms should include already. Also sync libpayload back up with what we have in coreboot. (I'm the original author of the clrsetbits_le32-definitions so I'm relicensing them to BSD here.) Change-Id: Ie4f7b9fdbdf9e8c0174427b4288f79006d56978b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37432 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/maxim/max77686/max77686.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c
index 54e3a6c912..cfbf912937 100644
--- a/src/drivers/maxim/max77686/max77686.c
+++ b/src/drivers/maxim/max77686/max77686.c
@@ -127,10 +127,10 @@ static int max77686_enablereg(unsigned int bus, enum max77686_regnum reg, int en
}
if (enable == REG_DISABLE) {
- clrbits_8(&read_data,
+ clrbits8(&read_data,
pmic->reg_enbitmask << pmic->reg_enbitpos);
} else {
- clrsetbits_8(&read_data,
+ clrsetbits8(&read_data,
pmic->reg_enbitmask << pmic->reg_enbitpos,
pmic->reg_enbiton << pmic->reg_enbitpos);
}
@@ -177,7 +177,7 @@ int max77686_volsetting(unsigned int bus, enum max77686_regnum reg,
}
vol_level /= (u32)pmic->vol_div;
- clrsetbits_8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos,
+ clrsetbits8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos,
vol_level << pmic->vol_bitpos);
ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, pmic->vol_addr, read_data);