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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-15 21:37:48 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-12-20 18:14:34 +0000
commit520717dff196e1d1ed61f72a8abadbc114ee6ba1 (patch)
tree5658d5fb27c6f5901c9b714fd1c6839ed36e28f9 /src/drivers
parentb9bd69e70ed355d89ff41d66ed7134338c5986fe (diff)
downloadcoreboot-520717dff196e1d1ed61f72a8abadbc114ee6ba1.tar.xz
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/amd/agesa/Makefile.inc4
-rw-r--r--src/drivers/amd/agesa/bootblock.c6
-rw-r--r--src/drivers/amd/agesa/romstage.c29
3 files changed, 7 insertions, 32 deletions
diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc
index 3c3c4fc621..4536fc9aca 100644
--- a/src/drivers/amd/agesa/Makefile.inc
+++ b/src/drivers/amd/agesa/Makefile.inc
@@ -19,12 +19,8 @@ romstage-y += state_machine.c
ramstage-y += state_machine.c
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
bootblock-y += bootblock.c
bootblock-y += cache_as_ram.S
-else
-cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S
-endif
postcar-y += exit_car.S
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c
index 91fcc6b994..7732f27fd5 100644
--- a/src/drivers/amd/agesa/bootblock.c
+++ b/src/drivers/amd/agesa/bootblock.c
@@ -16,6 +16,7 @@
#include <timestamp.h>
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/biosram.h>
+#include <arch/bootblock.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic.h>
@@ -29,6 +30,11 @@ static void set_early_mtrrs(void)
OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
}
+void bootblock_soc_early_init(void)
+{
+ bootblock_early_southbridge_init();
+}
+
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
enable_pci_mmconf();
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index ee4d45e95b..e8f4da2f28 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -15,7 +15,6 @@
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/romstage.h>
-#include <bootblock_common.h>
#include <cbmem.h>
#include <console/console.h>
#include <halt.h>
@@ -50,16 +49,10 @@ static void romstage_main(void)
u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24);
int cbmem_initted = 0;
- /* Enable PCI MMIO configuration. */
- if (CONFIG(ROMCC_BOOTBLOCK))
- amd_initmmio();
-
fill_sysinfo(cb);
if (initial_apic_id == 0) {
- if (CONFIG(ROMCC_BOOTBLOCK))
- timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
board_BeforeAgesa(cb);
@@ -70,8 +63,7 @@ static void romstage_main(void)
printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n",
initial_apic_id, cpuid_eax(1));
- if (!CONFIG(ROMCC_BOOTBLOCK))
- set_ap_entry_ptr(ap_romstage_main);
+ set_ap_entry_ptr(ap_romstage_main);
agesa_execute_state(cb, AMD_INIT_RESET);
@@ -112,10 +104,6 @@ static void ap_romstage_main(void)
struct sysinfo romstage_state;
struct sysinfo *cb = &romstage_state;
- /* Enable PCI MMIO configuration. */
- if (CONFIG(ROMCC_BOOTBLOCK))
- amd_initmmio();
-
fill_sysinfo(cb);
agesa_execute_state(cb, AMD_INIT_RESET);
@@ -126,22 +114,7 @@ static void ap_romstage_main(void)
halt();
}
-#if CONFIG(ROMCC_BOOTBLOCK)
-/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK
- * keeping changes in cache_as_ram.S easy to manage.
- */
-asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
-{
- romstage_main();
-}
-
-asmlinkage void ap_bootblock_c_entry(void)
-{
- ap_romstage_main();
-}
-#else
asmlinkage void car_stage_entry(void)
{
romstage_main();
}
-#endif