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| author | Werner Zeh <werner.zeh@siemens.com> | 2015-09-25 07:54:59 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2015-09-29 20:54:51 +0000 |
| commit | c947fee4791a8274ebb9128c43b0052d5cabe1b4 (patch) | |
| tree | b49934b5cbafe73508c4991f3688c1ab3fad03f7 /src/drivers | |
| parent | 387084cfb4e202af048f51842c24d443a8a0b927 (diff) | |
| download | coreboot-c947fee4791a8274ebb9128c43b0052d5cabe1b4.tar.xz | |
intel/fsp1.0: Get size of microcode during build time
Avoid specifying the size of the microcode in microcode_size.h.
Instead, the size will be determined during build time and
microcode_size.h will be generated. This way, the size does
not need to be adjusted by hand.
Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11709
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/intel/fsp1_0/Makefile.inc | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 11ff31aada..0ec52ecd91 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -23,8 +23,15 @@ romstage-y += fsp_util.c hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated) +ifneq ($(cpu_microcode-objs),) +$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin + printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \ + && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@ + +cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h +endif cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc ifeq ($(CONFIG_HAVE_FSP_BIN),y) @@ -45,3 +52,4 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif + |