intel: Use CF9 reset (part 2)

Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().

Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.

We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.

Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.

Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 16 insertions, 11 deletions

diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index bca9f71f19..c7d8722829 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -15,12 +15,12 @@
 
 #include <arch/acpi.h>
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <fsp/memmap.h>
 #include <fsp/romstage.h>
 #include <fsp/util.h>
 #include <lib.h> /* hexdump */
-#include <reset.h>
 #include <string.h>
 #include <timestamp.h>
 #include <security/vboot/vboot_common.h>
@@ -164,7 +164,8 @@ void raminit(struct romstage_params *params)
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 		printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
 		/* Failed S3 resume, reset to come up cleanly */
-		hard_reset();
+		/* FIXME: A "system" reset is likely enough: */
+		full_reset();
 #endif
 	}
 
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 8e8c24c96c..e1910e6ad5 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -22,6 +22,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/mtrr.h>
 #include <ec/google/chromeec/ec.h>
@@ -29,7 +30,6 @@
 #include <elog.h>
 #include <fsp/romstage.h>
 #include <mrc_cache.h>
-#include <reset.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <smbios.h>
@@ -134,7 +134,8 @@ void romstage_common(struct romstage_params *params)
 			printk(BIOS_DEBUG,
 			       "No MRC cache found in S3 resume path.\n");
 			post_code(POST_RESUME_FAILURE);
-			hard_reset();
+			/* FIXME: A "system" reset is likely enough: */
+			full_reset();
 		} else {
 			printk(BIOS_DEBUG, "No MRC cache found.\n");
 		}
@@ -164,7 +165,8 @@ void romstage_common(struct romstage_params *params)
 	/* Create romstage handof information */
 	if (romstage_handoff_init(
 			params->power_state->prev_sleep_state == ACPI_S3) < 0)
-		hard_reset();
+		/* FIXME: A "system" reset is likely enough: */
+		full_reset();
 }
 
 void after_cache_as_ram_stage(void)
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 1026c7982d..5eeea29504 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -18,6 +18,7 @@
 #include <assert.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <elog.h>
 #include <fsp/api.h>
@@ -25,7 +26,6 @@
 #include <memrange.h>
 #include <mrc_cache.h>
 #include <program_loading.h>
-#include <reset.h>
 #include <romstage_handoff.h>
 #include <string.h>
 #include <symbols.h>
@@ -80,7 +80,8 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
 			printk(BIOS_ERR,
 				"Failed to recover CBMEM in S3 resume.\n");
 			/* Failed S3 resume, reset to come up cleanly */
-			hard_reset();
+			/* FIXME: A "system" reset is likely enough: */
+			full_reset();
 		}
 	}
 
@@ -214,7 +215,8 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
 		 * returning error. Invoking a reset here saves time.
 		 */
 		if (!arch_upd->NvsBufferPtr)
-			hard_reset();
+			/* FIXME: A "system" reset is likely enough: */
+			full_reset();
 		arch_upd->BootMode = FSP_BOOT_ON_S3_RESUME;
 	} else {
 		if (arch_upd->NvsBufferPtr)
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
index f84d69cec5..98026f3362 100644
--- a/src/drivers/intel/fsp2_0/util.c
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -13,10 +13,10 @@
 
 #include <arch/io.h>
 #include <cbfs.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <lib.h>
-#include <reset.h>
 #include <string.h>
 
 static bool looks_like_fsp_header(const uint8_t *raw_hdr)
@@ -109,10 +109,10 @@ void fsp_handle_reset(uint32_t status)
 
 	switch (status) {
 	case FSP_STATUS_RESET_REQUIRED_COLD:
-		hard_reset();
+		full_reset();
 		break;
 	case FSP_STATUS_RESET_REQUIRED_WARM:
-		soft_reset();
+		system_reset();
 		break;
 	case FSP_STATUS_RESET_REQUIRED_3:
 	case FSP_STATUS_RESET_REQUIRED_4: