summaryrefslogtreecommitdiff
path: root/src/drivers
diff options
context:
space:
mode:
authorBarnali Sarkar <barnali.sarkar@intel.com>2017-08-17 11:52:39 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-26 16:30:31 +0000
commit0818a2a774e12f4522d139e8b6f3a39a8e1aa935 (patch)
treef0955666bc5410486f83a3bd44512a2582af8ca5 /src/drivers
parentb26e01a06718cc1a49a7c277c831b572a7301210 (diff)
downloadcoreboot-0818a2a774e12f4522d139e8b6f3a39a8e1aa935.tar.xz
soc/intel/skylake: Move SPI lock down config after resource allocation
This patch to ensures that coreboot is performing SPI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence SPI lock down programming has been moved right after pci resource allocation is donei, so that SPI registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set. Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers')
0 files changed, 0 insertions, 0 deletions