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authorDaisuke Nojiri <dnojiri@chromium.org>2017-09-21 17:52:36 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-04 20:55:12 +0000
commit47dffa59f35a46ada039dd86a20497caa8f518e8 (patch)
tree7a88e916aa974e06c53f2e99f4252e311818d977 /src/drivers
parent94b64431f3de19c79e7494d9ff25f9ebd1ab7cbc (diff)
downloadcoreboot-47dffa59f35a46ada039dd86a20497caa8f518e8.tar.xz
chromeec: Remove checks for EC in RO
This patch removes checks that ensure EC to be in RO for recovery boot. We do not need these checks because when recovery is requested automatically (as opposed to manually), we show 'broken' screen where users can only reboot the device or request recovery manually. If recovery is requested, Depthcharge will check whether EC is in RO or not and recovery switch was pressed or not. If it's a legitimate manual recovery, EC should be in RO. Thus, we can trust the recovery button state it reports. This patch removes all calls to google_chromeec_check_ec_image, which is called to avoid duplicate memory training when recovery is requested but EC is in RW. BUG=b:66516882 BRANCH=none CQ-DEPEND=CL:693008 TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/romstage.h1
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c15
2 files changed, 0 insertions, 16 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index dc1b6a66b0..892a653769 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -69,7 +69,6 @@ struct romstage_params {
* 30. FSP binary/FspNotify
*/
-void mainboard_check_ec_image(struct romstage_params *params);
void mainboard_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *memory_params);
void mainboard_romstage_entry(struct romstage_params *params);
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 4bc95c94f0..d79bc2f8c0 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -146,7 +146,6 @@ void romstage_common(struct romstage_params *params)
hard_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
- mainboard_check_ec_image(params);
}
}
@@ -200,20 +199,6 @@ __attribute__((weak)) struct chipset_power_state *fill_power_state(void)
return NULL;
}
-__attribute__((weak)) void mainboard_check_ec_image(
- struct romstage_params *params)
-{
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
- struct pei_data *pei_data;
-
- pei_data = params->pei_data;
- if (params->pei_data->boot_mode == ACPI_S0) {
- /* Ensure EC is running RO firmware. */
- google_chromeec_check_ec_image(EC_IMAGE_RO);
- }
-#endif
-}
-
/* Board initialization before and after RAM is enabled */
__attribute__((weak)) void mainboard_romstage_entry(
struct romstage_params *params)