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author | Aaron Durbin <adurbin@chromium.org> | 2016-10-28 17:32:24 -0500 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-31 19:34:20 +0100 |
commit | 8cd723bc0cb64f28b1009fd2fa55f6680a402b61 (patch) | |
tree | 97aad8d8164e39d12b0c710f6a16b59950a367c7 /src/drivers | |
parent | 9a2790e328c4cabefa201995aa4812be414d93c3 (diff) | |
download | coreboot-8cd723bc0cb64f28b1009fd2fa55f6680a402b61.tar.xz |
lib/prog_loaders: use common ramstage_cache_invalid()
All current implementations of ramstage_cache_invalid() were just
resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE
Kconfig option. Move that behavior to a single implementation
within prog_loaders.c which removes duplication.
Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17184
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/drivers')
-rw-r--r-- | src/drivers/intel/fsp1_1/romstage.c | 7 | ||||
-rw-r--r-- | src/drivers/intel/fsp2_0/stage_cache.c | 7 |
2 files changed, 0 insertions, 14 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index a95e5e602e..97379b2231 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -380,13 +380,6 @@ __attribute__((weak)) void raminit(struct romstage_params *params) die("ERROR - No RAM initialization specified!\n"); } -void ramstage_cache_invalid(void) -{ - if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) - /* Perform cold reset on invalid ramstage cache. */ - hard_reset(); -} - /* Display the memory configuration */ __attribute__((weak)) void report_memory_config(void) { diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 4469a7f3b5..434eae944a 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -28,10 +28,3 @@ void stage_cache_external_region(void **base, size_t *size) *size = 0; } } - -void ramstage_cache_invalid(void) -{ - if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) - /* Perform cold reset on invalid ramstage cache. */ - hard_reset(); -} |