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authorJulius Werner <jwerner@chromium.org>2019-08-16 15:35:39 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-11-20 10:10:48 +0000
commitf96d9051c2b39544300d35f64ce92502e1e230c0 (patch)
tree141966be0dedd056261528e55e05efde4b20b56d /src/drivers
parent63c444a69b98bc8a86719699423b3273cc5759e8 (diff)
downloadcoreboot-f96d9051c2b39544300d35f64ce92502e1e230c0.tar.xz
Remove MIPS architecture
The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/spi/cbfs_spi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c
index fca61004ff..c68b9061f8 100644
--- a/src/drivers/spi/cbfs_spi.c
+++ b/src/drivers/spi/cbfs_spi.c
@@ -53,7 +53,7 @@ static ssize_t spi_readat(const struct region_device *rd, void *b,
u64 speed; /* KiB/s */
int bps; /* Bits per second */
- speed = size * 1000 / usecs;
+ speed = size * (u64)1000 / usecs;
bps = speed * 8;
printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n",