diff options
author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2016-11-18 14:36:34 -0800 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-12-13 18:00:43 +0100 |
commit | ffc934d9440b5a8dabcedb4da0fa88d9a1e65e18 (patch) | |
tree | 2fd448d09b9a9c87ffbc6700f8ea25112f024e73 /src/drivers | |
parent | fa97cefbb3fad90573459e57845b658c9d3351a2 (diff) | |
download | coreboot-ffc934d9440b5a8dabcedb4da0fa88d9a1e65e18.tar.xz |
intel MMA: Enable MMA with FSP2.0
- Separate mma code for fsp1.1 and fsp2.0
and restructuring the code
- common code is placed in mma.c and mma.h
- mma_fsp<ver>.h and fsp<ver>/mma_core.c contains
fsp version specific code.
- whole MMA feature is guarded by CONFIG_MMA flag.
Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/17496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers')
-rw-r--r-- | src/drivers/intel/fsp1_1/Makefile.inc | 2 | ||||
-rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/romstage.h | 8 | ||||
-rw-r--r-- | src/drivers/intel/fsp1_1/mma_core.c | 51 | ||||
-rw-r--r-- | src/drivers/intel/fsp1_1/raminit.c | 1 | ||||
-rw-r--r-- | src/drivers/intel/fsp2_0/Makefile.inc | 2 | ||||
-rw-r--r-- | src/drivers/intel/fsp2_0/include/fsp/api.h | 7 | ||||
-rw-r--r-- | src/drivers/intel/fsp2_0/memory_init.c | 3 | ||||
-rw-r--r-- | src/drivers/intel/fsp2_0/mma_core.c | 46 |
8 files changed, 118 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4ea23f38ff..4088293e3f 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -31,6 +31,7 @@ romstage-y += romstage.c romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S romstage-y += stack.c romstage-y += stage_cache.c +romstage-$(CONFIG_MMA) += mma_core.c ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c ramstage-y += fsp_relocate.c @@ -39,6 +40,7 @@ ramstage-y += hob.c ramstage-y += ramstage.c ramstage-y += stage_cache.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c +ramstage-$(CONFIG_MMA) += mma_core.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 4683f5e5a2..dc1b6a66b0 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,6 +23,7 @@ #include <fsp/car.h> #include <fsp/util.h> #include <soc/intel/common/util.h> +#include <soc/intel/common/mma.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> /* chip_power_state */ @@ -80,6 +81,8 @@ void raminit(struct romstage_params *params); void report_memory_config(void); void romstage_common(struct romstage_params *params); asmlinkage void *romstage_main(FSP_INFO_HEADER *fih); +/* Initialize memory margin analysis settings. */ +void setup_mma(MEMORY_INIT_UPD *memory_upd); void *setup_stack_and_mtrrs(void); void soc_after_ram_init(struct romstage_params *params); void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -87,5 +90,8 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); void soc_pre_ram_init(struct romstage_params *params); +/* Update the SOC specific memory config param for mma. */ +void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, + struct mma_config_param *mma_cfg); #endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/mma_core.c b/src/drivers/intel/fsp1_1/mma_core.c new file mode 100644 index 0000000000..c0d100bbd3 --- /dev/null +++ b/src/drivers/intel/fsp1_1/mma_core.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <fsp/romstage.h> +#include <fsp/soc_binding.h> + +#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \ + { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } } + +int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size) +{ + const void *mma_hob_start; + const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID; + + mma_hob_start = get_first_guid_hob(&mma_results_guid); + if (!mma_hob_start) + return -1; + *mma_hob = GET_GUID_HOB_DATA(mma_hob_start); + *mma_hob_size = GET_HOB_LENGTH(mma_hob); + + if (!(*mma_hob_size) || !(*mma_hob)) + return -1; + return 0; +} + +void setup_mma(MEMORY_INIT_UPD *memory_cfg) +{ + struct mma_config_param mma_cfg; + + if (mma_locate_param(&mma_cfg)) { + printk(BIOS_DEBUG, "MMA: set up failed\n"); + return; + } + + soc_update_memory_params_for_mma(memory_cfg, &mma_cfg); + printk(BIOS_DEBUG, "MMA: set up completed successfully\n"); +} diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index eca8934aee..4b07ede96a 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -21,7 +21,6 @@ #include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> -#include <soc/intel/common/mma.h> #include <string.h> #include <timestamp.h> #include <vboot/vboot_common.h> diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index beeec7cee9..ad654b99eb 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -24,6 +24,7 @@ romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +romstage-$(CONFIG_MMA) += mma_core.c ramstage-y += debug.c ramstage-y += graphics.c @@ -36,6 +37,7 @@ ramstage-y += silicon_init.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +ramstage-$(CONFIG_MMA) += mma_core.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index a8445ba708..090b50d1da 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -16,6 +16,7 @@ #include <stddef.h> #include <stdint.h> #include <fsp/soc_binding.h> +#include <soc/intel/common/mma.h> #define FSP_SUCCESS EFI_SUCCESS @@ -47,6 +48,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callback after processing FSP notify */ void platform_fsp_notify_status(enum fsp_notify_phase phase); +/* Initialize memory margin analysis settings. */ +void setup_mma(FSP_M_CONFIG *memory_cfg); +/* Update the SOC specific memory config param for mma. */ +void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, + struct mma_config_param *mma_cfg); + /* * # DOCUMENTATION: * diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 283b179de1..63a5733a6b 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -313,6 +313,9 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, hdr->fsp_revision); + if (IS_ENABLED(CONFIG_MMA)) + setup_mma(&fspm_upd.FspmConfig); + /* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); diff --git a/src/drivers/intel/fsp2_0/mma_core.c b/src/drivers/intel/fsp2_0/mma_core.c new file mode 100644 index 0000000000..2e48e07fbb --- /dev/null +++ b/src/drivers/intel/fsp2_0/mma_core.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <fsp/soc_binding.h> + +static const uint8_t mma_results_uuid[16] = { 0x28, 0xe9, 0xf4, 0x08, + 0x5f, 0x0f, 0xd4, 0x46, + 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 }; + +int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size) +{ + *mma_hob_size = 0; + *mma_hob = fsp_find_extension_hob_by_guid(mma_results_uuid, + mma_hob_size); + + if (!(*mma_hob_size) || !(*mma_hob)) + return -1; + return 0; +} + +void setup_mma(FSP_M_CONFIG *memory_cfg) +{ + struct mma_config_param mma_cfg; + + if (mma_locate_param(&mma_cfg)) { + printk(BIOS_DEBUG, "MMA: set up failed\n"); + return; + } + + soc_update_memory_params_for_mma(memory_cfg, &mma_cfg); + printk(BIOS_DEBUG, "MMA: set up completed successfully\n"); +} |