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authorJonathan Zhang <jonzhang@fb.com>2020-01-16 11:16:45 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-06 08:19:59 +0000
commit8f89549d3c7d41643337662947cfdb2329bd030b (patch)
tree81d337d1e0bc655d82f47ba8808f42713942dc6a /src/drivers
parente425a09d6a0016e128373941ee1cf223a528a0fc (diff)
downloadcoreboot-8f89549d3c7d41643337662947cfdb2329bd030b.tar.xz
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP. This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base. The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/intel/fsp2_0/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 2624644fae..024a478eb6 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -56,7 +56,7 @@ config FSP_USE_REPO
depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \
SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \
SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \
- SOC_INTEL_DENVERTON_NS
+ SOC_INTEL_DENVERTON_NS || SOC_INTEL_XEON_SP
help
When selecting this option, the SoC must set FSP_HEADER_PATH
and FSP_FD_PATH correctly so FSP splitting works.