diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-12-18 15:56:44 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-19 19:47:02 +0000 |
| commit | f69d2d65745240627d42826c7abf1e576280d180 (patch) | |
| tree | 6e95057cb604022b22ff61ba6837e203882d730b /src/drivers | |
| parent | 9826d1b272a47d2a2c83eecafe399b96f882b4a5 (diff) | |
| download | coreboot-f69d2d65745240627d42826c7abf1e576280d180.tar.xz | |
drivers/mrc_cache: Make bootstate for SPI writes variable
The default time for writing MRC data to flash is at the exit of
BS_DEV_ENUMERATE but this is too early for some implementations.
Add an option to Kconfig for allowing a late option to be selected.
The timing of the late option is at the entry of BS_OS_RESUME_CHECK.
TEST=Select option and inspect console log on Kahlee
BUG=b:69614064
Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22937
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/mrc_cache/Kconfig | 9 | ||||
| -rw-r--r-- | src/drivers/mrc_cache/mrc_cache.c | 10 |
2 files changed, 16 insertions, 3 deletions
diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index 93ae6c6bf3..c367dcec95 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -29,4 +29,13 @@ config MRC_SETTINGS_VARIABLE_DATA bool default n +config MRC_WRITE_NV_LATE + bool + default n + help + MRC settings are normally written to NVRAM at BS_DEV_ENUMERATE-EXIT. + If a platform requires MRC settings written to NVRAM later than + normal, select this item. This will cause the write to occur at + BS_OS_RESUME_CHECK-ENTRY. + endif # CACHE_MRC_SETTINGS diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 3a9689645f..9732185646 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -574,8 +574,12 @@ static void update_mrc_cache(void *unused) } /* - * Ensures MRC training data is stored into SPI after PCI enumeration is done - * during BS_DEV_ENUMERATE-BS_ON_EXIT and lock down SPI protected ranges - * during BS_DEV_RESOURCES-BS_ON_EXIT. + * Ensures MRC training data is stored into SPI after PCI enumeration is done. + * Some implementations may require this to be later than others. */ + +#if IS_ENABLED(CONFIG_MRC_WRITE_NV_LATE) +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, update_mrc_cache, NULL); +#else BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, update_mrc_cache, NULL); +#endif |