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author | Matt DeVillier <matt.devillier@gmail.com> | 2020-03-14 16:22:01 -0500 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-16 14:41:57 +0000 |
commit | 2677e2dbf6a2733de6a7d6c4ff0975d8a2650e13 (patch) | |
tree | d8136a6a4131c141a5c0cc527919a1ca9ae87a89 /src/ec/51nb/npce985la0dx/npce985la0dx.c | |
parent | 93b0c7cfc632e7b57f1f4915886bf53397a12f25 (diff) | |
download | coreboot-2677e2dbf6a2733de6a7d6c4ff0975d8a2650e13.tar.xz |
ec/51nb: add support for NPCE985LA0DX EC
Add support for the NPCE985LA0DX, as used on the 51NB X210
(to be added in a follow-on commit, and from which this was extracted).
Original source: https://review.coreboot.org/c/coreboot/+/32531/37
Change-Id: I5798fad7fd18083cde1aa647fd91ca9c5ce963b7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Matthew Garrett <mjg59@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/ec/51nb/npce985la0dx/npce985la0dx.c')
-rw-r--r-- | src/ec/51nb/npce985la0dx/npce985la0dx.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/ec/51nb/npce985la0dx/npce985la0dx.c b/src/ec/51nb/npce985la0dx/npce985la0dx.c new file mode 100644 index 0000000000..0e0fcd1b90 --- /dev/null +++ b/src/ec/51nb/npce985la0dx/npce985la0dx.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <device/pnp.h> + +/* + * This embedded controller looks awfully like a Super I/O chip. LDNs 5 and 6 + * need to be enabled to turn on the keyboard and mouse controller, and LDN + * 0x11 needs to be enabled to turn on ACPI embedded controller functionality. + */ +static struct pnp_info dev_infos[] = { + { NULL, 0x05 }, { NULL, 0x06 }, { NULL, 0x11 } +}; + +static void ec_51nb_npce985la0dx_ops_enable(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(dev_infos), dev_infos); +} + +struct chip_operations ec_51nb_npce985la0dx_ops = { + CHIP_NAME("51NB EC") + .enable_dev = ec_51nb_npce985la0dx_ops_enable, +}; |