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authorVarun Joshi <varun.joshi@intel.corp-partner.google.com>2020-03-23 13:24:36 -0700
committerFurquan Shaikh <furquan@google.com>2020-04-10 01:57:27 +0000
commit9734325f4568c19d1ffc392084aa431a810a0709 (patch)
treecfd2967323c423c1894ad821d12590008250308e /src/ec/compal/ene932
parentc2e796290aa32cb22677cadf467209767cc03f93 (diff)
downloadcoreboot-9734325f4568c19d1ffc392084aa431a810a0709.tar.xz
soc/intel/tigerlake: Add support to initialize DDR4 Memory
Support to configure DDR4 memory variant. -Add support to read SPD data based on different memory topology. -Initialize FSP UPD's for DQ and DQS mapping. BUG=b:151702387 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39847 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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