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authorSam Lewis <sam.vr.lewis@gmail.com>2020-07-05 19:52:18 +1000
committerJulius Werner <jwerner@chromium.org>2020-07-07 21:48:30 +0000
commite69b1af925e489930f7b441840c7d8b9cb71be62 (patch)
treeb67a2ceb11c09194aaeb51120e4411a9c0dcbfdd /src/ec/ec.h
parent93d7bcbc67658fd1fb2ec084666283eb4b5dc728 (diff)
downloadcoreboot-e69b1af925e489930f7b441840c7d8b9cb71be62.tar.xz
armv7: mmu: Use 'tlbimva' to invalidate TLB entries
The tlbimvaa operation (invalidate unified TLB by MVA, all address space identifiers) is only available on armv7 processors that support Multiprocessing Extensions. When used on processors that do not support the extensions it causes an "undefined instruction" exception. This patch changes the MMU table entry filling code to use the tlbimva (invalidate unified TLB entry by MVA and address space identifier) operation for invalidating TLB entries, which is supported on all armv7 processors. As address space identifiers are not used in TLB entries in coreboot (all entries are set as global), these two operations can safely be used interchangeably. The ASID value supplied to the operation is not checked for global TLB entries. More information as well as the data formats for the tlbimvaa and tlbimva operations are detailed in the "ARM Architecture Reference Manual ARMv7-A" edition, issue "C.c" page B4-1747. TEST: Booted Beaglebone Black (my current in progress port) Change-Id: Ie7dfb4adab20dc7eecb1b20aa2ee6355215a1521 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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