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authorRaul E Rangel <rrangel@chromium.org>2021-05-12 17:03:40 -0600
committerPatrick Georgi <pgeorgi@google.com>2021-05-20 08:01:11 +0000
commit9bf32b9701ddabb3a584f47247416b4a16d1902b (patch)
tree6f10748d6984aa7a88577307a2ef8f6ebb6353a1 /src/ec/google/chromeec/acpi/cros_ec.asl
parenta9efed5fd90534b20b6739fa24e5a6339f67b827 (diff)
downloadcoreboot-9bf32b9701ddabb3a584f47247416b4a16d1902b.tar.xz
drivers/acpi: Add a chip driver to generate thermal zone
Given the following device tree entry: chip drivers/acpi/thermal_zone register "description" = ""CPU"" use chrome_ec as temperature_controller register "sensor_id" = "0" register "polling_period" = "10" register "critical_temperature" = "91" register "passive_config" = "{ .temperature = 85, }" register "use_acpi1_thermal_zone_scope" = "true" device generic 0 on end end It will generate the following: Scope (\_TZ) { ThermalZone (TM00) { Name (_STR, "CPU") // _STR: Description String Name (_RTV, Zero) // _RTV: Relative Temperature Values Name (_TZP, 0x64) // _TZP: Thermal Zone Polling Name (_CRT, 0x0E39) // _CRT: Critical Temperature Name (_PSV, 0x0DFD) // _PSV: Passive Temperature Name (_PSL, Package (0x10) // _PSL: Passive List { \_SB.CP00, \_SB.CP01, \_SB.CP02, \_SB.CP03, \_SB.CP04, \_SB.CP05, \_SB.CP06, \_SB.CP07, \_SB.CP08, \_SB.CP09, }) Name (_TC1, 0x02) // _TC1: Thermal Constant 1 Name (_TC2, 0x05) // _TC2: Thermal Constant 2 Name (_TSP, 0x14) // _TSP: Thermal Sampling Period Method (_TMP, 0, Serialized) // _TMP: Temperature { Return (\_SB.PCI0.LPCB.EC0.CREC.TMP (Zero)) } } } BUG=b:186166365 TEST=Boot guybrush to OS and verify thermal zone works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/ec/google/chromeec/acpi/cros_ec.asl')
0 files changed, 0 insertions, 0 deletions