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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2020-02-11 09:03:48 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-18 14:56:26 +0000 |
| commit | d346a19dedf28aecc4a2bce7ab9ee08323b63a1c (patch) | |
| tree | 87b176abb34eddb8ef9bf83e377dc9741bcf6c27 /src/ec/google/chromeec/ec_lpc.c | |
| parent | bda161b4b5744f98a8b5dfe71c584197f642e1ff (diff) | |
| download | coreboot-d346a19dedf28aecc4a2bce7ab9ee08323b63a1c.tar.xz | |
nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID
Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/ec/google/chromeec/ec_lpc.c')
0 files changed, 0 insertions, 0 deletions