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| author | Patrick Rudolph <siro@das-labor.org> | 2017-10-31 11:53:13 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-07-26 14:12:02 +0000 |
| commit | 5af2deae92abd1258a752f29fbe48c91458706c2 (patch) | |
| tree | 6c3a838c258fdc9fe3a2077fbf4ea2fcb4a229a4 /src/ec/google/chromeec/ec_lpc.c | |
| parent | 652c491917dce44be6fe0bdce475824af3d43c87 (diff) | |
| download | coreboot-5af2deae92abd1258a752f29fbe48c91458706c2.tar.xz | |
nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width
The bus width has to be encoded where the lower 3 bits are the bus width
in multiple of 8 and the following two bits give the error checking
bits in multiple of 8.
Hardcode to 64 bit as done on haswell.
TODO: Make it dynamic once there's ECC support.
Change-Id: I3b83a098205455b1c820d0436c6984938f261466
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/ec/google/chromeec/ec_lpc.c')
0 files changed, 0 insertions, 0 deletions