diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-11-20 20:28:18 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-11-22 19:10:26 +0000 |
| commit | 8788fd63952b50e4692efbf75a21bf0608e4c01c (patch) | |
| tree | c5b892728c2aafce88c00bc002ae3f0f31767939 /src/ec/google/chromeec/smm.h | |
| parent | beb0468fced261ced7ddbb8a1f982edcaf6cce8c (diff) | |
| download | coreboot-8788fd63952b50e4692efbf75a21bf0608e4c01c.tar.xz | |
chromeec: Change the API for hostevent/wake masks to handle 64-bit
ChromeEC is getting ready to bump up the hostevents and wake masks to
64-bits. The current commands to program hostevents/wake masks will
still operate on 32-bits only. A new EC host command will be added to
handle 64-bit hostevents/wake masks. In order to prevent individual
callers in coreboot from worrying about 32-bit/64-bit, the same API
provided by google/chromeec will be updated to accept 64-bit
parameters and return 64-bit values. Internally, host command handlers
will take care of masking these parameters/return values to
appropriate 32-bit/64-bit values.
BUG=b:69329196
Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/ec/google/chromeec/smm.h')
| -rw-r--r-- | src/ec/google/chromeec/smm.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/ec/google/chromeec/smm.h b/src/ec/google/chromeec/smm.h index 8265cddcfd..3d63a64bbf 100644 --- a/src/ec/google/chromeec/smm.h +++ b/src/ec/google/chromeec/smm.h @@ -25,20 +25,20 @@ void chromeec_smi_process_events(void); * Set wake masks according to sleep type, clear SCI and SMI masks, * and clear any pending events. */ -void chromeec_smi_sleep(int slp_type, uint32_t s3_mask, uint32_t s5_mask); +void chromeec_smi_sleep(int slp_type, uint64_t s3_mask, uint64_t s5_mask); /* * Set device event masks according to sleep type, * and clear any pending device events. */ -void chromeec_smi_device_event_sleep(int slp_type, uint32_t s3_mask, - uint32_t s5_mask); +void chromeec_smi_device_event_sleep(int slp_type, uint64_t s3_mask, + uint64_t s5_mask); /* * Provided the APMC command do the following while clearing pending events. * APM_CNT_ACPI_ENABLE: clear SMI mask. set SCI mask. * APM_CNT_ACPI_DISABLE: clear SCI mask. set SMI mask. */ -void chromeec_smi_apmc(int apmc, uint32_t sci_mask, uint32_t smi_mask); +void chromeec_smi_apmc(int apmc, uint64_t sci_mask, uint64_t smi_mask); #endif /* _EC_GOOGLE_CHROMEEC_SMM_H */ |