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| author | Patrick Rudolph <siro@das-labor.org> | 2017-10-31 11:36:55 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-07-26 14:11:38 +0000 |
| commit | 652c491917dce44be6fe0bdce475824af3d43c87 (patch) | |
| tree | b680131d04445d73a70282fe2a7e95d7ca904705 /src/ec/google/chromeec | |
| parent | 8ba9e8cf63f92902cdb71eb5c4d3b3ea579380f4 (diff) | |
| download | coreboot-652c491917dce44be6fe0bdce475824af3d43c87.tar.xz | |
nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops
On desktop boards the PPD bit of MRS register MR0 is set and thus
DLL_Off mode shouldn't be used, as enforced by datasheet
2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.17.1.
Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/ec/google/chromeec')
0 files changed, 0 insertions, 0 deletions