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author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2020-09-22 00:48:36 +0800 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2020-09-23 06:14:22 +0000 |
commit | 83f0c699c773afe7a81831e1f980ded1e36fb821 (patch) | |
tree | 5b1ce2003bbdfe30968cb288c79af28fac9a4b06 /src/ec/google/chromeec | |
parent | 8b1ee26ac1012e43bfc50665fe95c20caf3c8bb8 (diff) | |
download | coreboot-83f0c699c773afe7a81831e1f980ded1e36fb821.tar.xz |
ec/google/chromeec: set DPTC power parameter at OS startup
set DPTC power parameter per clamshell/tablet mode
after EC OP region is accessible.
BUG=b:157943445
BRANCH=zork
TEST=1. emerge-zork coreboot
2. power on DUT in tablet mode then check "thermctl_limit"
will change automatically
Change-Id: Ic3e1119881790c34f5649986334b4e3cecafc02b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/ec/google/chromeec')
-rw-r--r-- | src/ec/google/chromeec/acpi/ec.asl | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index e2fa2ded87..d12274f8c0 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -159,6 +159,17 @@ Device (EC0) // Initialize LID switch state Store (LIDS, \LIDS) + +#ifdef EC_ENABLE_AMD_DPTC_SUPPORT + /* + * Per the device mode (clamshell or tablet) to initialize + * the thermal setting on OS startup. + */ + If (CondRefOf (\_SB.DPTC)) { + \_SB.DPTC() + } +#endif + } /* Read requested temperature and check against EC error values */ |