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authorKenji Chen <kenji.chen@intel.com>2014-09-26 03:14:57 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-02 17:27:48 +0200
commite383feb7c8e1b46639c32df9a11fac6cf3d62403 (patch)
treea9f78cc9d181b5c20ea608a8080673cdab07c181 /src/ec/google
parentc373f503dbbfc2a70e91f576fac01f66126556c2 (diff)
downloadcoreboot-e383feb7c8e1b46639c32df9a11fac6cf3d62403.tar.xz
Broadwell: Synchronize for power management with FRC
Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration. BUG=chrome-os-partner:31424 TEST=Build an image, and check the procedure and recommended setting is applied correctly. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4 Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2 Original-Reviewed-on: https://chromium-review.googlesource.com/219994 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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