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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-17 15:14:38 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-20 13:52:14 +0000
commit07841c2a2a930383dfd56d5adc966d0efaafec66 (patch)
tree321714a5ea901a2fba7a84ce04430a81d311e8f7 /src/ec/google
parent7d640e2ac791d9847e70ecfc41940ce7d104c06a (diff)
downloadcoreboot-07841c2a2a930383dfd56d5adc966d0efaafec66.tar.xz
src/ec: Drop __PRE_RAM__ and __SMM__ guards
For files built in ramstage and smm -classes, testing for !__PRE_RAM__ is redundant. All chip_operations are exluded with use of DEVTREE_EARLY in static devicetree, so garbage collection will take care of the !__SMM__ cases. Change-Id: Id7219848d6f5c41c4a9724a72204fa5ef9458e43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/ec/google')
-rw-r--r--src/ec/google/chromeec/ec.c4
-rw-r--r--src/ec/google/chromeec/ec_i2c.c2
-rw-r--r--src/ec/google/chromeec/ec_lpc.c5
-rw-r--r--src/ec/google/chromeec/ec_spi.c2
4 files changed, 0 insertions, 13 deletions
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 5a2630ecb0..ed53c61b81 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -719,8 +719,6 @@ retry:
return cec_cmd.cmd_code;
}
-#ifndef __PRE_RAM__
-
int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen,
uint8_t *buffer, int len, int is_read)
{
@@ -1109,8 +1107,6 @@ int google_ec_running_ro(void)
return (ec_image_type == EC_IMAGE_RO);
}
-#endif /* ! __PRE_RAM__ */
-
/**
* Check if EC/TCPM is in an alternate mode or not.
*
diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c
index c3e1968c95..dc012fcd9e 100644
--- a/src/ec/google/chromeec/ec_i2c.c
+++ b/src/ec/google/chromeec/ec_i2c.c
@@ -252,10 +252,8 @@ int google_chromeec_command(struct chromeec_command *cec_command)
#endif /* CONFIG_EC_GOOGLE_CHROMEEC_I2C_PROTO3 */
-#ifndef __PRE_RAM__
u8 google_chromeec_get_event(void)
{
printk(BIOS_ERR, "%s: Not supported.\n", __func__);
return 0;
}
-#endif
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index 7dae6a2e17..feea9dd483 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -415,8 +415,6 @@ int google_chromeec_command(struct chromeec_command *cec_command)
return -1;
}
-#ifndef __PRE_RAM__
-#ifndef __SMM__
static void lpc_ec_init(struct device *dev)
{
if (!dev->enabled)
@@ -471,8 +469,6 @@ struct chip_operations ec_google_chromeec_ops = {
.enable_dev = enable_dev,
};
-#endif /* __SMM__ */
-
static int google_chromeec_data_ready(u16 port)
{
return google_chromeec_status_check(port, EC_LPC_CMDR_DATA,
@@ -502,4 +498,3 @@ u8 google_chromeec_get_event(void)
/* Event (or 0 if none) is returned directly in the data byte */
return read_byte(EC_LPC_ADDR_ACPI_DATA);
}
-#endif
diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c
index 3611814b66..c47d419647 100644
--- a/src/ec/google/chromeec/ec_spi.c
+++ b/src/ec/google/chromeec/ec_spi.c
@@ -115,10 +115,8 @@ int google_chromeec_command(struct chromeec_command *cec_command)
return crosec_command_proto(cec_command, crosec_spi_io, &slave);
}
-#ifndef __PRE_RAM__
u8 google_chromeec_get_event(void)
{
printk(BIOS_ERR, "%s: Not supported.\n", __func__);
return 0;
}
-#endif