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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-05-15 16:45:21 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-27 17:25:57 +0000 |
| commit | 97c7c6bbb6c9dd2ef4f917c3c4c16a8ff0de5d9f (patch) | |
| tree | 30a67e32ce77415b5b4f8734029a2037e4a7a6d5 /src/ec/purism/librem/acpi | |
| parent | b66ee5507c4c2395868a5cd350dc8a7eb46542fd (diff) | |
| download | coreboot-97c7c6bbb6c9dd2ef4f917c3c4c16a8ff0de5d9f.tar.xz | |
cpu/intel/model_2065x: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/ec/purism/librem/acpi')
0 files changed, 0 insertions, 0 deletions