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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-30 13:07:47 -0500
committerTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-31 20:54:56 +0200
commitc00f4d669dd03bf5a4ee8c255bb71fc86f229239 (patch)
tree74a4ac484e9dccddac66e46c725a92ecb9d58179 /src/ec
parentc094d9961144871c472698c41ce634e58abb6a32 (diff)
downloadcoreboot-c00f4d669dd03bf5a4ee8c255bb71fc86f229239.tar.xz
nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
During power on from cold (S5) state, numerous MCEs are generated before DRAM training starts, e.g. during HT link training. Clear these MCEs before DRAM training start, and report any MCEs generated during DRAM training. Change-Id: I7d047571242e5bd041e4aac22c1ec1d7d26ef0e6 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14191 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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