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| author | Alexandru Gagniuc <alexandrux.gagniuc@intel.com> | 2016-05-03 11:02:14 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-06 18:56:44 +0200 |
| commit | 5ff7031f729a319f35c9acdc1526a115a925398e (patch) | |
| tree | 22eca843808ea0800ba6c4782ed4ed940a11a765 /src/ec | |
| parent | bdd921c7720d372399ab57796eb9dcba48530249 (diff) | |
| download | coreboot-5ff7031f729a319f35c9acdc1526a115a925398e.tar.xz | |
intel/amenia: Configure the bridge to ChromeEC in the bootblock
Communication with ChromeEC, which is on the LPC bus, is needed early
on for vboot purposes. I'm not sure if Google wants to have the
interface available in bootblock or romstage, so we're confguring it
in the bootblock.
The bridge is automatically reconfigured during ramstage in a way in
which we don't get duplicate windows opened upt to LPC.
Change-Id: I77887e881d23f655495dec2687394409a5bb8cf5
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14588
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/ec')
0 files changed, 0 insertions, 0 deletions