diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-06-13 11:07:04 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-06-13 21:14:08 +0000 |
| commit | 6ff848aaf811789460f7bf6f0f89f71aa7fe8bee (patch) | |
| tree | 09510e4d5c326065e4743557e10568a1286b6f4b /src/ec | |
| parent | de666dc9b86452d5efbda70aa2364877d2fcd449 (diff) | |
| download | coreboot-6ff848aaf811789460f7bf6f0f89f71aa7fe8bee.tar.xz | |
ec/google/wilco: Read back from EC RAM after S0ix entry
We are seeing an EC interrupt after setting the EC RAM offset that
indicates that the EC should transition to S0ix mode and this is
preventing the kernel from going into S0ix on the first try.
As a workaround if we read back from the EC RAM while still in the
_DSM handler it seems to prevent this problem.
BUG=b:130644677
BRANCH=sarien
TEST=ensure s0ix entry works on the first try with sarien
Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec')
| -rw-r--r-- | src/ec/google/wilco/acpi/ec.asl | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 4fa887b1b4..532f421780 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -154,6 +154,12 @@ Device (EC0) If (Arg0) { Printf ("EC Enter S0ix") W (CSEX, One) + + /* + * Read back from EC RAM after enabling S0ix + * to prevent EC from aborting S0ix entry. + */ + R (EVT1) } Else { Printf ("EC Exit S0ix") W (CSEX, Zero) |