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authorDavid Hendricks <dhendrix@chromium.org>2014-11-03 17:42:09 -0800
committerAaron Durbin <adurbin@chromium.org>2015-04-10 16:47:44 +0200
commit627b3bd2b09e4daf40001f2a7833df3ef2a257b2 (patch)
tree1ab02371b56f7cdf7477cfcc6c61ae602fff5531 /src/include/boot
parentceaabc94efec339f75732dd7bf72c51f8dc52941 (diff)
downloadcoreboot-627b3bd2b09e4daf40001f2a7833df3ef2a257b2.tar.xz
cbtables: Add RAM config information
This adds the RAM config code to the coreboot tables. The purpose is to expose this information to software running at higher levels, e.g. to print the RAM config coreboot is using as part of factory tests. The prototype for ram_code() is in boardid.h since they are closely related and will likely have common code. BUG=chrome-os-partner:31728 BRANCH=none TEST=tested w/ follow-up CLs on pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400 Original-Reviewed-on: https://chromium-review.googlesource.com/227248 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 77dd5fb9347b53bb8a64ad22341257fb3be0c106) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ibe7044cafe0a61214ac2d7fea5f7255b2c11829b Reviewed-on: http://review.coreboot.org/9438 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/include/boot')
-rw-r--r--src/include/boot/coreboot_tables.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index db55adaa36..56394733ce 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -276,6 +276,13 @@ struct lb_macs {
struct mac_address mac_addrs[0];
};
+#define LB_TAG_RAM_CODE 0x0028
+struct lb_ram_code {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t ram_code;
+};
+
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */