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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2017-01-19 15:25:15 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-01-23 15:23:32 +0100 |
| commit | 0f6d10ba8f8f711f2ff7fa5c8f306e18a42b8974 (patch) | |
| tree | 0489fe249228966a54dd716f20992456bfdef745 /src/include/boot_device.h | |
| parent | 35d7d361e33bea244a6ca4b270061f6ab92f7cd8 (diff) | |
| download | coreboot-0f6d10ba8f8f711f2ff7fa5c8f306e18a42b8974.tar.xz | |
google/pyro: Update DPTF settings
1. Update DPTF CPU/TSR1 passive trigger points.
CPU passive point: 80
TSR1 passive point: 46
2. Update DPTF TRT Sample Period
TSR1: 8s
BUG=chrome-os-partner:62133
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I8fcf750ac17b8894ed3c8704eec62f5071d9cf24
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18174
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/boot_device.h')
0 files changed, 0 insertions, 0 deletions