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| author | Wisley Chen <wisley.chen@quantatw.com> | 2017-09-01 14:33:06 +0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-09-13 19:31:26 +0000 |
| commit | f7d0f02b367199603e554fb424164a9a31d67afc (patch) | |
| tree | 3ac1b5d9aa6c169612a844f16959bc06f683c4f9 /src/include/bootstate.h | |
| parent | b92f6d36dfc7f6dc2a9fb0551739feb3dc3ea04c (diff) | |
| download | coreboot-f7d0f02b367199603e554fb424164a9a31d67afc.tar.xz | |
mb/google/soraka: Update DPTF parameters
Cloned from baseboard/dptf.asl and update the parameters for soraka.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU: passive point:85, critial point:100
TSR0: passive point:55, critial point:65
TSR1: passive point:58, critial point:70
TSR2: passive point:60, critial point:75
TSR3: passive point:60, critial point:75
2. Set PL1 Max to 7W, and PL1 Min 4.5W
3. Change sampling period of thermal relationship table (TRT) setting
CPU: 5 seconds
TSR0: 30 seconds
TSR1: 30 seconds
TSR2: 8 seconds
TSR3: 8 Seconds
BUG=b:65467566
TEST=build, boot on soraka, and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590
Reviewed-on: https://review.coreboot.org/21453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/include/bootstate.h')
0 files changed, 0 insertions, 0 deletions