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| author | Aaron Durbin <adurbin@chromium.org> | 2015-03-06 23:17:33 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-04-22 17:55:08 +0200 |
| commit | bd74a4b2d25268f7035a4478da31f27baac2aecc (patch) | |
| tree | 56740c02fe396df8ccf9fc2e7401542deeebf453 /src/include/cbmem.h | |
| parent | cac50506238507328b8ea0f4abd458869803e6c2 (diff) | |
| download | coreboot-bd74a4b2d25268f7035a4478da31f27baac2aecc.tar.xz | |
coreboot: common stage cache
Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.
Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/include/cbmem.h')
| -rw-r--r-- | src/include/cbmem.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 615510b1fb..8c61cb2a18 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -78,6 +78,8 @@ #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_SPINTABLE 0x59175917 +#define CBMEM_ID_STAGEx_META 0x57a9e000 +#define CBMEM_ID_STAGEx_CACHE 0x57a9e100 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_WIFI_CALIBRATION 0x57494649 |