summaryrefslogtreecommitdiff
path: root/src/include/console
diff options
context:
space:
mode:
authorVikram Narayanan <vikram186@gmail.com>2012-01-23 01:44:44 +0530
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-01-23 22:50:56 +0100
commit0713ca3f8493ee89103b4826137bd64f59c88933 (patch)
treebc137ad8444b98cd5a468e09a21de1b80b836edd /src/include/console
parent15370ca0688beff07cfbdf69ef47b0284227ef03 (diff)
downloadcoreboot-0713ca3f8493ee89103b4826137bd64f59c88933.tar.xz
post code: Replaced hard-coded post code with macro
Added a macro in the post code list, which replaces hard coded value in cpu/x86/cache/cache.c Change-Id: I27cb27827272584a8a17a41c111e2dc155196a97 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/572 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include/console')
-rw-r--r--src/include/console/post_codes.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index a72da69bd5..1d12e5ad3f 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -106,6 +106,13 @@
#define POST_CONSOLE_BOOT_MSG 0x40
/**
+ * \brief Before enabling the cache
+ *
+ * Going to enable the cache
+ */
+#define POST_ENABLING_CACHE 0x60
+
+/**
* \brief Devices have been enumerated
*
* Bus scan, and device enumeration has completed.