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author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-06 18:01:04 -0800 |
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committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-09 17:16:09 +0100 |
commit | 0ca2a0654ca4b403e8a54d558bce07a862820a9d (patch) | |
tree | 86c845b441c8ae4824bf6178943148ec94441c6d /src/include/cpu/amd/amdfam10_sysconf.h | |
parent | 75d8d8da47a3cc759d7395f5b0ef91ba13a59e51 (diff) | |
download | coreboot-0ca2a0654ca4b403e8a54d558bce07a862820a9d.tar.xz |
src/include: Fix unsigned warnings
Fix warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
BRANCH=none
BUG=None
TEST=Build and run on Galileo Gen2
Change-Id: I23d9b4b715aa74acc387db8fb8d3c73bd5cabfaa
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18607
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include/cpu/amd/amdfam10_sysconf.h')
-rw-r--r-- | src/include/cpu/amd/amdfam10_sysconf.h | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h index ade78c8b75..bff65ec917 100644 --- a/src/include/cpu/amd/amdfam10_sysconf.h +++ b/src/include/cpu/amd/amdfam10_sysconf.h @@ -21,41 +21,41 @@ #include <cpu/x86/msr.h> struct p_state_t { - unsigned corefreq; - unsigned power; - unsigned transition_lat; - unsigned busmaster_lat; - unsigned control; - unsigned status; + unsigned int corefreq; + unsigned int power; + unsigned int transition_lat; + unsigned int busmaster_lat; + unsigned int control; + unsigned int status; }; struct amdfam10_sysconf_t { //ht - unsigned hc_possible_num; - unsigned pci1234[HC_POSSIBLE_NUM]; - unsigned hcdn[HC_POSSIBLE_NUM]; - unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type - unsigned sbdn; - unsigned sblk; + unsigned int hc_possible_num; + unsigned int pci1234[HC_POSSIBLE_NUM]; + unsigned int hcdn[HC_POSSIBLE_NUM]; + unsigned int hcid[HC_POSSIBLE_NUM]; //record ht chain type + unsigned int sbdn; + unsigned int sblk; - unsigned nodes; - unsigned ht_c_num; // we only can have 32 ht chain at most - unsigned ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable - unsigned io_addr_num; - unsigned conf_io_addr[HC_NUMS]; - unsigned conf_io_addrx[HC_NUMS]; - unsigned mmio_addr_num; - unsigned conf_mmio_addr[HC_NUMS*2]; // mem and pref mem - unsigned conf_mmio_addrx[HC_NUMS*2]; - unsigned segbit; - unsigned hcdn_reg[HC_NUMS]; // it will be used by get_pci1234 + unsigned int nodes; + unsigned int ht_c_num; // we only can have 32 ht chain at most + unsigned int ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable + unsigned int io_addr_num; + unsigned int conf_io_addr[HC_NUMS]; + unsigned int conf_io_addrx[HC_NUMS]; + unsigned int mmio_addr_num; + unsigned int conf_mmio_addr[HC_NUMS*2]; // mem and pref mem + unsigned int conf_mmio_addrx[HC_NUMS*2]; + unsigned int segbit; + unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234 msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5 - unsigned needs_update_pstate_msrs; + unsigned int needs_update_pstate_msrs; - unsigned bsp_apicid; + unsigned int bsp_apicid; int enabled_apic_ext_id; - unsigned lift_bsp_apicid; + unsigned int lift_bsp_apicid; int apicid_offset; void *mb; // pointer for mb related struct |