diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/include/cpu/amd/amdfam15.h | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/include/cpu/amd/amdfam15.h')
| -rw-r--r-- | src/include/cpu/amd/amdfam15.h | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 271af8aef5..18feaffa45 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -19,9 +19,6 @@ #include <types.h> #include <cpu/x86/msr.h> -#define MCG_CAP 0x00000179 -# define MCA_BANKS_MASK 0xff -#define MC0_CTL 0x00000400 #define MC0_STATUS 0x00000401 # define MCA_STATUS_HI_VAL BIT(63 - 32) # define MCA_STATUS_HI_OVERFLOW BIT(62 - 32) @@ -189,30 +186,4 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg) return MCA_ERRTYPE_UNKNOWN; } -#define MSR_SMM_BASE 0xC0010111 -#define MSR_TSEG_BASE 0xC0010112 -#define MSR_SMM_MASK 0xC0010113 -# define SMM_TSEG_VALID (1 << 1) -# define SMM_TSEG_WB (6 << 12) -#define HWCR_MSR 0xC0010015 -# define SMM_LOCK (1 << 0) -#define NB_CFG_MSR 0xC001001f - -#define MMIO_CONF_BASE 0xC0010058 -# define MMIO_BUS_RANGE_SHIFT 2 -# define MMIO_RANGE_EN (1 << 0) - -#define PSTATE_0_MSR 0xC0010064 - -#define LS_CFG_MSR 0xC0011020 -#define IC_CFG_MSR 0xC0011021 -#define DC_CFG_MSR 0xC0011022 -#define CU_CFG_MSR 0xC0011023 -#define CU_CFG2_MSR 0xC001102A - -#define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 - -#define CORE_PERF_BOOST_CTRL 0x15C - #endif /* CPU_AMD_FAM15_H */ |