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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-29 06:38:46 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-30 08:15:30 +0000 |
| commit | 33d0fb8d346512e1b6819fa70cb17212ea014336 (patch) | |
| tree | f8831b2f4f65e7edefa90520fed54d0778c1dba7 /src/include/cpu/amd/msr.h | |
| parent | 3aa17f76044f92dd772cd2833fa8f30031e17f35 (diff) | |
| download | coreboot-33d0fb8d346512e1b6819fa70cb17212ea014336.tar.xz | |
AGESA,binaryPI: Add compatibility wrapper for romstage entry
This simplifies transition and reviews towards C environment
bootblock by allowing single cache_as_ram.S file to be used.
Change-Id: I231972982e5ca6d0c08437693edf926b0eaf9ee1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37352
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/cpu/amd/msr.h')
0 files changed, 0 insertions, 0 deletions