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| author | Nils Jacobs <njacobs8@hetnet.nl> | 2010-11-01 15:20:27 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-01 15:20:27 +0000 |
| commit | 76890dde1428741a7c91732b04cc3c95ada9c321 (patch) | |
| tree | e57fa1bfddf42afcf6a20cd8581f84ff896080b3 /src/include/cpu/amd | |
| parent | 96446239346128308a9f8500c4018aae579a876d (diff) | |
| download | coreboot-76890dde1428741a7c91732b04cc3c95ada9c321.tar.xz | |
Change Geode GX2 to use the auto DRAM detect code from Geode LX.
Also, change the GX2 boards to use it.
Add a processor speed setting function in human readable MHz and remove
the useless and broken PLLMSR settings (the processor speed was hardcoded
to 366MHz in pll_reset.c).
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/amd')
| -rw-r--r-- | src/include/cpu/amd/gx2def.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index eaaeca4328..b89f7e69ab 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -413,6 +413,13 @@ #define AES_GLD_MSR_PM (MSR_AES + 0x2004) #define AES_CONTROL (MSR_AES + 0x2006) +/* from MC spec */ +#define MIN_MOD_BANKS 1 +#define MAX_MOD_BANKS 2 +#define MIN_DEV_BANKS 2 +#define MAX_DEV_BANKS 4 +#define MAX_COL_ADDR 17 + /* more fun stuff */ #define BM 1 /* Base Mask - map power of 2 size aligned region */ #define BMO 2 /* BM with an offset */ |