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authorRonald G. Minnich <rminnich@chromium.org>2012-06-05 14:41:27 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-13 16:07:45 +0100
commit8b93059eccedc528443c06eb86c58bd320dca203 (patch)
tree65b3dd93170d53a6ba8dfb9ce63a347e95339f5b /src/include/cpu/cpu.h
parent455f4b432835828e82531adf967b9c7d8fc812dc (diff)
downloadcoreboot-8b93059eccedc528443c06eb86c58bd320dca203.tar.xz
Pass the CPU index as a parameter to startup.
This addition is in support of future multicore support in coreboot. It also will allow us to remove some asssembly code. The CPU "index" -- i.e., its order in the sequence in which cores are brought up, NOT its APIC id -- is passed into the secondary start. We modify the function to specify regparm(0). We also take this opportunity to do some cleanup: indexes become unsigned ints, not unsigned longs, for example. Build and boot on a multicore system, with pcserial enabled. Capture the output. Observe that the messages Initializing CPU #0 Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 appear exactly as they do prior to this change. Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1820 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/include/cpu/cpu.h')
-rw-r--r--src/include/cpu/cpu.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index a9369fbf76..e8ea096a6c 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -4,10 +4,10 @@
#include <arch/cpu.h>
#if !defined(__ROMCC__)
-void cpu_initialize(void);
+void cpu_initialize(unsigned int cpu_index);
struct bus;
void initialize_cpus(struct bus *cpu_bus);
-void __attribute__((regparm(0))) secondary_cpu_init(void);
+void __attribute__((regparm(0))) secondary_cpu_init(unsigned int cpu_index);
#if CONFIG_HAVE_SMI_HANDLER
void smm_init(void);