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authorShaunak Saha <shaunak.saha@intel.com>2017-07-18 00:19:33 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-08 19:01:04 +0000
commitbd427803ab18576462c2c179c94ec0fec819221c (patch)
treea441902068336e7d83bd2ad94efc2153e00bd1a1 /src/include/cpu/intel/reset.h
parentaf896d071b5d0c6ffabc1f4a5cda1429fb6754b6 (diff)
downloadcoreboot-bd427803ab18576462c2c179c94ec0fec819221c.tar.xz
soc/intel/common/block: Common ACPI
This patch adds the common acpi code.ACPI code is very similar accross different intel chipsets.This patch is an effort to move those code in common place so that it can be shared accross different intel platforms instead of duplicating for each platform. We are removing the common acpi files in src/soc/intel/common. This removes the acpi.c file which was previously in src/soc/common/acpi. The config for common acpi is SOC_INTEL_COMMON_BLOCK_ACPI which can be defined in SOC's Kconfig file in order to use the common ACPI code. This patch also includes the changes in APL platform to use the common ACPI block. TEST= Tested the patch as below: 1.Builds and system boots up with the patch. 2.Check all the ACPI tables are present in /sys/firmware/acpi/tables 3.Check SCI's are properly working as we are modifying the function to override madt. 4.Extract acpi tables like DSDT,APIC, FACP, FACS and decompile the by iasl and compare with good known tables. 5.Execute the extracted tables in aciexec to check acpi methods are working properly. Change-Id: Ib6eb6fd5366e6e28fd81bc22d050b0efa05a2e5d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/include/cpu/intel/reset.h')
-rw-r--r--src/include/cpu/intel/reset.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/src/include/cpu/intel/reset.h b/src/include/cpu/intel/reset.h
new file mode 100644
index 0000000000..9cf6168a7c
--- /dev/null
+++ b/src/include/cpu/intel/reset.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef CPU_INTEL_RESET_H
+#define CPU_INTEL_RESET_H
+
+/* Reset control port */
+#define RST_CNT 0xcf9
+#define FULL_RST (1 << 3)
+#define RST_CPU (1 << 2)
+#define SYS_RST (1 << 1)
+
+#endif /* CPU_INTEL_RESET_H */