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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 22:54:22 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-11 18:42:07 +0100 |
commit | 9b9915284f5070c6f664fa36495ae831e95ea819 (patch) | |
tree | 3b078aeab72924c2a0981d0c06adc17d8afe3573 /src/include/cpu/intel/romstage.h | |
parent | 5ecc41b0c9226486da71d6aa95a505877f0fdaeb (diff) | |
download | coreboot-9b9915284f5070c6f664fa36495ae831e95ea819.tar.xz |
intel/sandybridge: Use common ACPI S3 recovery
Fix regression, S3 resume not working on sandy/ivy after commit
9d6f365 ACPI S3: Remove HIGH_MEMORY_SAVE where possible
There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup
being done after the backup copy. Moving to RELOCATABLE_RAMSTAGE fixes
this delay by removing need of this backup entirely.
Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15248
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/cpu/intel/romstage.h')
0 files changed, 0 insertions, 0 deletions