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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-14 13:02:41 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-22 06:37:50 +0000 |
| commit | f5c0d612966d1ab3e8c2f1d1ae1de9ae2438bbab (patch) | |
| tree | 2441da4161b6e11f38c17dd2b18c98ee431db4ad /src/include/cpu/intel/smm_reloc.h | |
| parent | 75396f67aa6f1f24007714c2c959c3eefe7d0124 (diff) | |
| download | coreboot-f5c0d612966d1ab3e8c2f1d1ae1de9ae2438bbab.tar.xz | |
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined
for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/cpu/intel/smm_reloc.h')
| -rw-r--r-- | src/include/cpu/intel/smm_reloc.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index cb196fcd82..bef8d4eed7 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -14,7 +14,29 @@ #ifndef __INTEL_SMM_RELOC_H__ #define __INTEL_SMM_RELOC_H__ +#include <console/console.h> #include <types.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> + +struct smm_relocation_params { + uintptr_t ied_base; + size_t ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t prmrr_base; + msr_t prmrr_mask; + msr_t uncore_prmrr_base; + msr_t uncore_prmrr_mask; + /* + * The smm_save_state_in_msrs field indicates if SMM save state + * locations live in MSRs. This indicates to the CPUs how to adjust + * the SMMBASE and IEDBASE + */ + int smm_save_state_in_msrs; +}; + +extern struct smm_relocation_params smm_reloc_params; struct ied_header { char signature[10]; @@ -42,4 +64,36 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_ bool cpu_has_alternative_smrr(void); + +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +static inline void write_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); +} + +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); +} + #endif |