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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-20 14:27:09 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-24 09:53:26 +0000 |
| commit | 062b92ef654a97648380a1a9a9fe34229ee76e31 (patch) | |
| tree | 0c64f02b62684a040ac0844c8af9c160fcaff1b2 /src/include/cpu/intel | |
| parent | 10ae1cf2cda38e681849dcc9e6e86ee3330a8b17 (diff) | |
| download | coreboot-062b92ef654a97648380a1a9a9fe34229ee76e31.tar.xz | |
cpu/intel/common: rework code previously moved to common cpu code
Rework the code moved to common code in CB:46274. This involves
simplification by using appropriate helpers for MSR and CPUID, using
macros instead of plain values for MSRs and cpu features and adding
documentation to the header.
Change-Id: I7615fc26625c44931577216ea42f0a733b99e131
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/include/cpu/intel')
| -rw-r--r-- | src/include/cpu/intel/msr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 9dbea776dd..a2165f365a 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -10,5 +10,6 @@ #define AESNI_LOCK (1 << 0) #define MSR_PIC_MSG_CONTROL 0x2e +#define TPR_UPDATES_DISABLE (1 << 10) #endif /* CPU_INTEL_MSR_H */ |