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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2017-11-26 15:34:20 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-11 01:10:51 +0000 |
| commit | f6bbc603fadf4fdb6c9c86775739ff1b32ab5f1e (patch) | |
| tree | 71bde50e867fdbfd66fb1fba65aa179f8827dfcc /src/include/cpu/intel | |
| parent | a78319ba26c01c3bd5a3573c448ea39394d81eaf (diff) | |
| download | coreboot-f6bbc603fadf4fdb6c9c86775739ff1b32ab5f1e.tar.xz | |
intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c
Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include/cpu/intel')
| -rw-r--r-- | src/include/cpu/intel/speedstep.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 59336ed0c6..4b556b758b 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -40,6 +40,7 @@ #define IA32_PERF_CTL 0x199 #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 +#define MSR_EBC_FREQUENCY_ID 0x2c #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 |