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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-25 22:58:23 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-26 00:46:35 +0200 |
| commit | 3f8989ebbce4305541c6df569d283f76029ae724 (patch) | |
| tree | 25252b3dc8c636a3af2264a414c6085e3471bf7e /src/include/cpu/intel | |
| parent | 05e740fc40e409dcf8d592f4bbeaf87dc92140c5 (diff) | |
| download | coreboot-3f8989ebbce4305541c6df569d283f76029ae724.tar.xz | |
Revamp Intel microcode update code
- add GPLv2 + copyright header after talking to Ron
- "bits" in struct microcode served no real purpose but
getting its address taken. Hence drop it
- use asm volatile instead of __asm__ volatile
- drop superfluous wrmsr (that seems to be harmless but
is still wrong) in read_microcode_rev
- use u32 instead of unsigned int where appropriate
- make code usable both in bootblock and in ramstage
- drop ROMCC style print_debug statements
- drop microcode update copy in Sandybridge bootblock
Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/928
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/include/cpu/intel')
| -rw-r--r-- | src/include/cpu/intel/microcode.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index f2f044ab87..4139c01e82 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -1 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if !defined(__ROMCC__) void intel_update_microcode(const void *microcode_updates); +#endif |