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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-17 17:22:51 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-02 21:57:51 +0000
commit6a8ce0d250f4dbaa2f253e566cf76e20f753d131 (patch)
tree47e81bd475098c3b8e411eafc677bc76951bd2db /src/include/cpu/intel
parent8168046432b5bd3da213f7b00beb80543123bab3 (diff)
downloadcoreboot-6a8ce0d250f4dbaa2f253e566cf76e20f753d131.tar.xz
cpu/intel/car: Prepare for some POSTCAR_STAGE support
The file cache_as_ram_ht.inc is used across a variety of CPUs and northbridges. We need to split it anyway for future C_ENVIRONMENT_BOOTBLOCK and verstage work. Split and rename the files, remove code that is globally implemented in POSTCAR_STAGE framework already. Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/cpu/intel')
-rw-r--r--src/include/cpu/intel/romstage.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index 3a9e98934b..eace57e558 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -22,6 +22,8 @@ void mainboard_romstage_entry(unsigned long bist);
*/
void *setup_stack_and_mtrrs(void);
+void platform_enter_postcar(void);
+
/* romstage_main is called from the cache-as-ram assembly file to prepare
* CAR stack guards.*/
asmlinkage void *romstage_main(unsigned long bist);