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authorLee Leahy <leroy.p.leahy@intel.com>2017-03-07 17:45:12 -0800
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-13 17:23:37 +0100
commit6a566d7fbee8e81fa22916a29339e5991872edfb (patch)
tree21840b8f2965439422e809ab56f9ef19cdccf4bd /src/include/cpu/intel
parentd0f26fcea2fdab02d9b9fc1fceb9e782694a55bc (diff)
downloadcoreboot-6a566d7fbee8e81fa22916a29339e5991872edfb.tar.xz
src/include: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters Changed a few comments to reduce line length. File src/include/cpu/amd/vr.h was skipped. TEST=Build and run on Galileo Gen2 Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18687 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include/cpu/intel')
-rw-r--r--src/include/cpu/intel/l2_cache.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h
index 587e43369f..35059ff74f 100644
--- a/src/include/cpu/intel/l2_cache.h
+++ b/src/include/cpu/intel/l2_cache.h
@@ -83,10 +83,12 @@
#define L2CMD_MESI_I 0
extern int calculate_l2_latency(void);
-extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command);
+extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way,
+ u8 command);
extern int read_l2(u32 address);
extern int write_l2(u32 address, u32 data);
-extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low);
+extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high,
+ u32 data_low);
extern int calculate_l2_cache_size(void);
extern int calculate_l2_physical_address_range(void);
extern int set_l2_ecc(void);