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authorStefan Reinauer <stepan@coreboot.org>2010-12-11 22:14:44 +0000
committerStefan Reinauer <stepan@openbios.org>2010-12-11 22:14:44 +0000
commit2a27b20226a2fd593bfd5f6a0eee45418233fe04 (patch)
tree950aa542d9266c1cb004d2346062609c37ed16b3 /src/include/cpu/intel
parent2b9070a610132eaf61dca67e7713c082903fffef (diff)
downloadcoreboot-2a27b20226a2fd593bfd5f6a0eee45418233fe04.tar.xz
factor out cpu power management base into a separate file. And fix a bug in
model_1067x Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/intel')
-rw-r--r--src/include/cpu/intel/speedstep.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
new file mode 100644
index 0000000000..0fa5244181
--- /dev/null
+++ b/src/include/cpu/intel/speedstep.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* MWAIT coordination I/O base address. This must match
+ * the \_PR_.CPU0 PM base address.
+ */
+#define PMB0_BASE 0x510
+
+/* PMB1: I/O port that triggers SMI once cores are in the same state.
+ * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
+ */
+#define PMB1_BASE 0x800
+